A 14b 150 MS/s 140 mW 2.0 mm(2) 0.13 mu m CMOS A/D converter for software-defined radio systems

作者：Choi Hee Cheol; Yoo Pil Seon; Ahn Gil Cho^*; Lee Seung Hoon

来源：International Journal of Circuit Theory and Applications, 2011, 39(2): 135-147.

DOI：10.1002/cta.622

• thermal noise
• scaling-down factor
• high-resolution
• CMOS
• ADC

This work proposes a 14 b 150 MS/s CMOS A/D converters (ADC) for software-defined radio systems requiring simultaneously high-resolution, low-power, and small chip area at high speed. The proposed calibration-free ADC employs a wide-band low-noise input sample-and-hold amplifier (SHA) along with a four-stage pipelined architecture optimizing scaling-down factors for the sampling capacitance and the input trans-conductance of amplifiers in each stage to minimize thermal noise effect and power consumption. A signal-insensitive 3-D fully symmetric layout achieves a 14 b level resolution by reducing a capacitor mismatch of three MDACs. The prototype ADC in a 0.13 mu m 1P8M CMOS technology demonstrates a measured differential nonlinearity (DNL) and integral nonlinearity within 0.81LSB and 2.83LSB at 14 b, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64 and 61 dB and a maximum spurious-free dynamic range of 71 and 70 dB at 120 and 150 MS/s, respectively. The ADC with an active die area of 2.0 mm(2) consumes 140 mW at 150 MS/s and 1.2 V.

• 出版日期2011-2