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摘要
In the digital design area, quantum-dot cellular automata (QCA) has become a promising alternative to the CMOS technology. As a basic unit in digital arithmetic circuits, the full adder has been extensively studied in the development of QCA technology. This paper presents two novel full adder implementations using QCA, which outperform other designs with fewer cells, smaller areas, shorter latency and lower cost. The two full adders share many properties in common and differ only in cell numbers. Concretely speaking, a latency of 0.75 clock cycle, area of 0.01 mu m(2) and cost weighted 0.0056 is implemented using only 28 and 31 normal cells, respectively. To illustrate the superiority of our design in complex structures, ripple carry adder circuits of 4-bit, 8-bit and 16-bit size have been implemented using the proposed 1-bit full adder. Simulation results show that the proposed design also has good stability and scalability in different circuit size, resulting in significant improvements in terms of number of cells, area, cost compared to designs in other studies, while maintaining an equally well clock latency with the best previous one. The proposed designs in this paper have been functionally verified with the QCADesigner tool.
- 出版日期2018-9
- 单位合肥工业大学
