A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called "Adaptively Assigned Breaking-Off Condition (A(2)BC)"

作者：Enomoto Tadayoshi^*; Kobayashi Nobuaki

来源：IEICE TRANSACTIONS ON ELECTRONICS, 2013, E96C(4): 424-432.

DOI：10.1587/transele.E96.C.424

• multimedia
• H.264/AVC
• motion estimation
• DVFS
• power dissipation
• DC/DC level converter

A motion estimation (ME) multimedia processor was developed by employing dynamic voltage and frequency scaling (DVFS) technique to greatly reduce the power dissipation. To make full use of the advantages of DVFS technique, a fast motion estimation (ME) algorithm was also developed. It can adaptively predict the optimum supply voltage and the optimum clock frequency before ME process starts for each macro-block for encoding. Power dissipation of the 90-nm CMOS DVFS controlled multimedia processor, which contained an absolute difference accumulator as well as a small on-chip DC/DC level converter, a minimum value detector and DVFS controller, was reduced to 38.48 mu W, which was only 3.261% that of a conventional multimedia processor.

• 出版日期2013-4