Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes

作者：Garcia Herrero F; Canet M J; Valls J^*

来源：Circuits, Systems, and Signal Processing, 2013, 32(2): 727-741.

DOI：10.1007/s00034-012-9481-3

• Galois field
• Non-binary low-density parity-check (LDPC) codes
• VLSI
• Decoder

A VLSI architecture for the generalized bit-flipping decoding algorithm for non-binary low-density parity-check codes is proposed in this paper. The tentative decoding steps of the algorithm have been modified to avoid computing and storing a matrix of dimension Nx2 (q) , for a code (N,K) over GF(2 (q) ), reducing its complexity with a minimal penalization of its performance, less than 0.05 dB compared with the original algorithm. The architecture was synthesized using a 90 nm standard cell library, for the (837,723) non-binary code over GF(2(5)), requiring 590220 xor gates and achieving a throughput of 89 Mbps. Additionally, it was implemented in a Virtex-VI FPGA device with a cost of 4070 slices and a throughput of 44.6 Mbps.

• 出版日期2013-4