A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller

作者：Shikata Akira^*; Sekimoto Ryota; Yoshioka Kentaro; Kuroda Tadahiro; Ishikuro Hiroki

来源：IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2013, E96A(2): 443-452.

DOI：10.1587/transfun.E96.A.443

• analog-to-digital converter
• successive approximation
• asynchronous
• differential flip-flop

This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flip-flop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4-10 bit resolution and 0.4-1 V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4 V single power supply voltage. At 10 bit mode and 1 V operation, up to 10 MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.

• 出版日期2013-2