A 3.2-GHz down-spread spectrum clock generator using a nested fractional topology

作者：Yang Ching Yuan^*; Chang Chih Hsiang; Wong Wen Ger

来源：IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2008, E91A(2): 497-503.

DOI：10.1093/ietfec/e91-a.2.497

• spread spectrum clock generation
• fractional phase-locked loop
• delay-locked loop
• phase compensation
• fractional divider

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N-1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2 GHz, the measured peak power reduction is around 16 dB for a deviation of 0.37% and a frequency modulation of 33 kHz. The circuit occupies 1.4 x 1.4 mm(2) in a 0.18-mu m CMOS process and consumes 52 row.

• 出版日期2008-2
• 单位中国科学院电工研究所