Black box polynomial identity testing of generalized depth-3 arithmetic circuits with bounded top fan-in

作者：Karnin Zohar S^*; Shpilka Amir

来源：Combinatorica, 2011, 31(3): 333-364.

DOI：10.1007/s00493-011-2537-3

In this paper we consider the problem of determining whether an unknown arithmetic circuit, for which we have oracle access, computes the identically zero polynomial. This problem is known as the black-box polynomial identity testing (PIT) problem. Our focus is on polynomials that can be written in the form, where each h (i) is a polynomial that depends on only rho linear functions, and each g (i) is a product of linear functions (when h (i) = 1, for each i, then we get the class of depth-3 circuits with k multiplication gates, also known as I I pound I (k) pound circuits, but the general case is much richer). When max (i) (deg(h (i) center dot g (i) )) = d we say that f is computable by a I I pound I (k; pound d;rho) circuit. We obtain the following results.
A deterministic black-box identity testing algorithm for I I pound I (k; pound d;rho) circuits that runs in quasi-polynomial time (for rho=polylog(n+d)). In particular this gives the first black-box quasi-polynomial time PIT algorithm for depth-3 circuits with k multiplication gates.
A deterministic black-box identity testing algorithm for read-k I I pound I pound circuits (depth-3 circuits where each variable appears at most k times) that runs in time. In particular this gives a polynomial time algorithm for k=O(1).
Our results give the first sub-exponential black-box PIT algorithm for circuits of depth higher than 2. Another way of stating our results is in terms of test sets for the underlying circuit model. A test set is a set of points such that if two circuits get the same values on every point of the set then they compute the same polynomial. Thus, our first result gives an explicit test set, of quasi-polynomial size, for I I pound I (k; pound d;rho) circuits (when rho=polylog(n+d)). Our second result gives an explicit polynomial size test set for read-k depth-3 circuits.
The proof technique involves a construction of a family of affine subspaces that have a rank-preserving property that is inspired by the construction of linear seeded extractors for affine sources of Gabizon and Raz [9], and a generalization of a theorem of [8] regarding the structure of identically zero depth-3 circuits with bounded top fan-in.

• 出版日期2011-5