A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests

作者：Kaeriyama Shunichi^*; Kajita Mikihiro; Mizuno Masayuki

来源：IEICE - Transactions on Electronics, 2011, E94C(1): 102-109.

DOI：10.1587/transele.E94.C.102

• clock generator
• duty ratio
• frequency synthesis
• I/Q balance
• jitter
• timing margin

A 4-phase clock generator, which can dynamically change clock frequencies, duty ratios and I/Q balance, is proposed for on-chip timing margin testing. The clock generator macro is integrated into the microprocessor chip of the supercomputer SX-9, which is fabricated with a 65 nm CMOS technology. It demonstrates frequency syntheses of 1.68 GHz to 3 GHz range, an instant frequency change capability for timing margin testing, duty ratio and I/Q balance adjustments of -12.5 ps to 9.4 ps with a 3.125 ps step resolution.

• 出版日期2011-1