Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration

作者：Niitsu Kiichi^*; Sugimori Yasufumi; Kohama Yoshinori; Osada Kenichi; Irie Naohiko; Ishikuro Hiroki; Kuroda Tadahiro

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, 19(10): 1902-1907.

DOI：10.1109/TVLSI.2010.2056711

• CMOS integrated circuits
• high-speed interconnect
• low-power design
• SiP
• wireless interconnect

This paper discusses analysis and techniques formitigating interference of an inductive-coupling inter-chip link. Electromagnetic interference from power/signal lines and to SRAM circuits was simulated and measured. In order to verify the interference, test chips were designed and fabricated using 65-nm CMOS technology. The measurement results revealed that: 1) interference from power lines depends on the shape of the power lines; 2) interference from signal lines can be canceled by increasing transmitter power by only 9%; and 3) interference with SRAM circuits is less important than other issues under ordinary conditions. Based on the measurement results, interference mitigation techniques are proposed and investigated.

• 出版日期2011-10