A LOW OFFSET COMPARATOR FOR HIGH SPEED LOW POWER ADC

作者：Zhu, Zhangming^*; Wang, Weitie; Guan, Yuheng; Liu, Shubin; Xiao, Yu; Liu, Lianxi; Yang, Yintang

来源：Journal of Circuits, Systems, and Computers, 2013, 22(7): 1350061.

DOI：10.1142/S0218126613500618

• Low offset
• latched comparator
• Monte Carlo analysis
• positive feedback

A novel low offset, high speed, low power comparator architecture is proposed in this paper. In order to achieve low or set, both offset cancellation and dynamic amplifier techniques are adopted. Active resistors are chosen to implement the static amplifier circuit to obtain reduction in equivalent input referred offset voltage as well as to increase the circuit speed. The comparator is designed in TSMC 0.18 mu m CMOS process. Monte Carlo simulation shows that the comparator has the or set voltage as low as 0.3 mV at 1 sigma at 250 MHz while dissipates 342 mu W from a 1.8 V supply.

• 出版日期2013-8
• 单位西安电子科技大学