A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS

作者：Gin**urg Brian P^*; Ramaswamy Srinath M; Rentala Vijay; Seok Eunyoung; Sankaran Swaminathan; Haroun Baher

来源：IEEE Journal of Solid-State Circuits, 2014, 49(4): 984-995.

DOI：10.1109/JSSC.2014.2298033

• CMOS
• input compression point
• mixer
• mm-wave
• noise figure
• phased array
• radar
• wireless.

This paper presents a 160 GHz center frequency pulsed 65 nm CMOS transceiver for short range radar applications. Four phased array transceivers were implemented in a single chip with antennas implemented in a BGA package. The implemented transmitter is capable of producing pulses of 100 ps widths (>20 GHz RF bandwidth) at a 160 GHz carrier frequency. The measured effective isotropic radiated power ( EIRP) is 18.8 dBm for continuous wave outputs. The analog beam forming receiver achieves an overall gain of 42.5 dB, -14 dBm, IP1db, 7 GHz bandwidth, and a noise figure of 22.5 dB. The sliding window time-dilation baseband relaxes the output data rate and subsequent digital processing requirements. Fine grained duty cycling reduces power dissipation. The entire chip consumes 2.2W from 1.2/1.4 V supplies in a 65 nm digital CMOS process.

• 出版日期2014-4