A Clock Regenerator using Two 2nd Order Sigma-Delta Modulators for Wide Range of Dividing Ratio

作者：Oh Seung Wuk^*; Kim Sang Ho; Im Sang Soon; Ahn Yong Sung; Kang Jin Ku

来源：Journal of Semiconductor Technology and Science, 2012, 12(1): 10-17.

DOI：10.5573/JSTS.2012.12.1.10

• High-Definition Multimedia Interface (HDMI)
• Transition Minimized Differential Signaling (TMDS)
• Cycle Time Stamp (CTS)
• Sigma-Delta Modulator (SDM)
• Multi-Modulus Divider (MMD)
• audio clock regenerator
• phase locked loop (PLL)

This paper presents a clock regenerator using two 2nd order Sigma-Delta (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different Sigma-Delta modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 mu m CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.

• 出版日期2012-3