A 24-GHz power amplifier with P-sat of 15.9 dBm and PAE of 14.6 % using standard 0.18 mu m CMOS technology

作者：Lin Yo Sheng^*; Chang Jing Ning

来源：Analog Integrated Circuits and Signal Processing, 2014, 79(3): 427-435.

DOI：10.1007/s10470-014-0290-4

• CMOS
• 24 GHz
• Power amplifier
• Saturated output power
• Power added efficiency

A 24 GHz power amplifier for direct-conversion transceiver using standard 0.18 mu m CMOS technology is reported. The three-stage power amplifier comprises two cascaded cascode stages for high power gain, followed by a common-source stage for high power linearity. To increase the saturated output power (P-sat) and power-added efficiency (PAE), the output stage adopts a Wilkinson-power-divider- and combiner-based two-way power dividing and combining architecture. The power amplifier consumes 163.8 mW and achieves power gain (S-21) of 22.8 dB at 24 GHz. The corresponding 3-dB bandwidth of S-21 is 4.2 GHz, from 22.7 to 26.9 GHz. At 24 GHz, the power amplifier achieves P-sat of 15.9 dBm and maximum PAE of 14.6 %, an excellent result for a 24 GHz CMOS power amplifier. In addition, the measured output 1-dB compression point (OP1dB) is 7 dBm at 24 GHz. These results demonstrate the proposed power amplifier architecture is very promising for 24 GHz short-range communication system applications.

• 出版日期2014-6