A 0.009-1.4-GHz Frequency Synthesizer With Suppressed Transients During VCO Band Switching

作者：Lam Jerry^*; Riley Tom; Filiol Norman M; Rogers John W M; Plett Calvin

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2015, 62(12): 1129-1133.

DOI：10.1109/TCSII.2015.2468914

• Analog integrated circuits
• BiCMOS integrated circuits
• frequency synthesizer
• phase-locked loop (PLL)
• radio-frequency integrated circuits
• subthreshold CMOS circuits
• tunable circuits and devices
• voltage-controlled oscillators (VCOs)

This brief presents a 0.009-1.4-GHz frequency synthesizer that is able to compensate for changes in the frequency tuning range, due to temperature variations, by switching voltage-controlled oscillator (VCO) bands with minimal phase and frequency errors, without cycle slipping and without introducing any phase offsets. This is accomplished by a subthreshold capacitor bank switching circuit that causes the gradual addition of capacitance slowly enough to allow the loop to adjust the VCO control voltage to compensate. The additional circuitry uses less than 0.001 mm(2) of silicon area and has minimal power consumption and minimal effects on the synthesizer's phase noise when fully switched. The synthesizer used to demonstrate this was implemented in a 0.18-mu m SiGe BiCMOS process and achieves 365-fs integrated jitter at 1.05 GHz, with a total power consumption of 81 mW. Measurements of the capacitor bank switching circuit shows that it prevents cycle slipping during band switching and reduces the maximum frequency deviation by 99.3%.

• 出版日期2015-12