A 36 V Programmable Instrumentation Amplifier With Sub-20 mu V Offset and a CMRR in Excess of 120 dB at All Gain Settings

作者：Schaffer Viola^*; Snoeij Martijn F; Ivanov Mikhail V; Trifonov Dimitar T

来源：IEEE Journal of Solid-State Circuits, 2009, 44(7): 2036-2046.

DOI：10.1109/JSSC.2009.2021921

• Chopper
• CMRR
• high-voltage CMOS design
• industrial instrumentation
• instrumentation amplifier
• programmable gain

A 36 V capable programmable gain instrumentation amplifier (PGA) is presented with sub-20 mu V offset, sub-0.2 mu V/degrees C offset drift and a common-mode rejection (CMRR) that exceeds 120 dB at all gain settings without any trimming. It is the first 36 V capable precision PGA implemented high-voltage CMOS process, which, in addition, incorporates several additional functions, such as the detection of input and output fault conditions, provisions for improving system-level settling time and an input switch network. All op-amps used in the PGA employ chopper stabilization with a notch filter that removes chopping glitches, leading to low offset and drift and no 1/f noise. The PGA has a total of 22 gain steps (binary steps between 1/8 to 128, each with an optional multiplying factor of 1 or 1375) with better than 0.1% gain accuracy, < 0.001% nonlinearity and sub-2 ppm/C gain drift. The input switch network, in addition to acting as a 2-channel multiplexer, also enables various system-level diagnostic features. The PGA is implemented in a 0.35 mu m CMOS process with a 36 V extension, has a 3.6 x 2.4 mm chip area and consumes a total quiescent current of 3 mA.