An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count

作者：Lin Ying Zu^*; Chang Soon Jyh; Liu Yen Ting; Liu Chun Cheng; Huang Guan Ying

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57(8): 1829-1837.

DOI：10.1109/TCSI.2009.2037403

• Asynchronous analog-to-digital converter (ADC)
• Binary-search analog-to-digital converter (ADC)
• successive approximation register (SAR)

This paper reports an asynchronous binary-search analog-to-digital converter (ADC) with reference range prediction. An original N-bit binary-search ADC requires 2(N) - 1 comparators while the proposed one only needs 2N - 1 ones. Compared to the (high speed, high power) flash ADC and (low speed, low power) successive approximation register ADC, the proposed architecture achieves the balance between power consumption and operation speed. The proof-of-concept 5-bit prototype only consists of a passive track-and-hold circuit, a reference ladder, 9 comparators, 56 switches and 26 static logic gates. This compact ADC occupies an active area of 120 x 50 mu m(2) and consumes 1.97 mW from a 1-V supply. At 800 MS/s, the effective number of bits is 4.40 bit and the effective resolution bandwidth is 700 MHz. The resultant figure of merit is 116 fJ/conversion-step.

• 出版日期2010-8