A design of high-speed-sampling stochastic flash analog-to-digital converter utilizing device mismatch

作者：Ham Hyunju^*; Matsuoka Toshimasa; Wang Jun; Taniguchi Kenji

来源：IEEJ Transactions on Electronics, Information and Systems, 2011, 131(11): 1848-1857.

DOI：10.1541/ieejeiss.131.1848

• Calibration circuits
• CMOS
• CMOS processs
• Conversion speed
• Device mismatch
• Flash Analog-to-digital Converters
• FLASH-ADC
• Mismatch
• Non-Linearity
• Power supply
• Quantization errors
• Reduction techniques

A stochastic flash analog-to-digital converter (SF-ADC) utilizing device mismatch is designed using a 65-nm CMOS process. Since the proposed SF-ADC uses thresholds determined by the input-referred comparator offsets, the large input-referred offsets are allowed. The quantization error and non-linearity of SF-ADC are demonstrated, and the input range is enlarged by using non-linearity reduction technique. At 1.6 GS/s sampling, the designed ADC achieves 34.7dB SFDR and 29.0dB SNDR without any calibration circuits despite the large input-referred offset of 102 mV. At this conversion speed, it consumes 134 mW with a 1.2-V power supply.

• 出版日期2011