Design for Small Delay Test - A Simulation Study

作者：Kampmann Matthias^*; Hellebrand Sybille

来源：Microelectronics Reliability, 2018, 80: 124-133.

DOI：10.1016/j.microrel.2017.11.019

• Faster-than-at-speed-test
• Small Delay Faults
• BIST
• X-tolerant compaction
• X-masking

Early Life Failures (ELFs) are becoming an important reliability issue in state-of-the-art technologies. ELFs can be indicated by Small Delay Faults (SDFs), however, some SDFs may not be detectable even with modern at-speed tests. For these hidden SDFs, Faster-than-at-Speed Test (FAST) provides a solution. However, FAST imposes new challenges on the test method. Unknown logic values (X-values) are a major challenge in FAST, due to the increased frequencies. A special Design-for-FAST architecture relying on an accordingly adjusted scan configuration and a simple, but efficient X-masking scheme can support X-tolerant compaction in the context of FAST. This work analyzes the trade-offs of this concept within the framework of a standard industrial workflow and presents a comprehensive case study. Simulation results indicate that for some designs, the conventional synthesis workflow does not produce optimal circuit behavior under FAST. In these cases, the Design-for-FAST approach can increase the fault efficiency, while at the same time reducing the amount of X-values in the test responses considerably.

• 出版日期2018-1