A 12-bit 350 MS/s Single-Channel Pipeline ADC with 75 dB SFDR in 0.18 mu m. BiCMOS

作者：Sun, Jie^*; Wu, Jianhui

来源：Journal of Circuits, Systems, and Computers, 2019, 28(3): 1950044.

DOI：10.1142/S0218126619500440

• Pipeline ADC
• hetero-junction bipolar transistor
• negative bootstrap power
• residue amplifier
• reference buffer
• comparator
• start-up

A 12-bit 350 MS/s ADC with 75 dB SFDR fabricated in 0.18 mu m SiGe BiCMOS process is presented. To improve the power efficiency, the ADC employs a novel residue amplifier (RA) by exploiting the hetero-junction bipolar transistor (HBT). We also propose a fast comparator to save time for the residue settling of pipeline stages. A fully integrated reference buffer with "negative bootstrap power" (NBP) is proposed to improve both high power supply rejection ratio (PSRR) and ground supply rejection ratio (GSRR). A bandgap reference (BGR) with ultra-low leakage current start-up loop is also presented. The measured results show that with Nyquist input, the SFDR achieves 75 dB and 63 dB SNDR up to 350 MS/s and consumes 180 mW (only ADC core) with 580 fj/cov Waldon FOM.

• 出版日期2019-3
• 单位东南大学