Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding

作者：Lin Chen Hung^*; Chen Chun Yu; Wu An Yeu

来源：IEEE Transactions on Very Large Scale Integration Systems, 2011, 19(2): 305-318.

DOI：10.1109/TVLSI.2009.2032553

• Maximum a posteriori algorithm (MAP)
• multistandard platform
• turbo codes

Most of advanced wireless standards, such as WiMAX and LTE, have adopted different convolutional turbo code (CTC) schemes with various block sizes and throughput rates. Thus, a reconfigurable and scalable hardware accelerator for multistandard CTC decoding is necessary. In this paper, we propose scalable maximum a posteriori algorithm (MAP) processor designs which can support both single-binary (SB) and double-binary (DB) CTC decoding, and handle arbitrary block sizes for high throughput CTC decoding. We first propose three combinations of parallel-window (PW) and hybrid-window (HW) MAP decoding. Moreover, the computational modules and storages of the dual-mode (SB/DB) MAP decoding are designed to achieve a high area utilization. To verify the proposed approaches, a 1.28 mm(2) dual-mode 2PW-1HW MAP processor is implemented in 0.13 mu m CMOS process. The prototyping chip achieves a maximum throughput rate of 500 Mb/s at 125 MHz with an energy efficiency of 0.19 nJ/bit and an area efficiency of 3.13 bits/mm(2). For the multistandard systems, the expected throughput rates of the WiMAX and LTE CTC schemes is achieved by using five dual-mode 2PW-1HW MAP processors.

• 出版日期2011-2
• 单位中国科学院电工研究所