Achieving low-V-T Ni-FUSICMOS by ultra-thin Dy2O3 capping of hafnium silicate dielectrics

作者：Veloso A^*; Yu H Y; Chang S Z; Adelmann C; Onsia B; Brus S; Demand M; Lauwers A; O'; Sullivan B J; Singanamalla R; Pourtois G; Lehnen P; Van Elshocht S; De Meyer K; Jurczak M; Absil P P; Biesemans S

来源：IEEE Electron Device Letters, 2007, 28(11): 980-983.

DOI：10.1109/LED.2007.908505

• cap layers
• high-k dielectrics
• low-V-T CMOS
• Ni-Fully Silicided (Ni-FUSI) metal gates

This letter reports that the effective work eWF) of Ni-Fully Silicided (Ni-FUSI) devices with HfSiON gate dielectrics can be modulated toward the silicon conduction band-edge by deposition of an ultra-thin Dy2O3 cap layer on the host dielectric. The obtained eWF depends on the deposited cap layer thickness and the Ni-FUSI phase, with 10 angstrom Dy2O3 cap resulting in Delta eWF approximate to 400 meV and final eWF approximate to 4.08 eV for NiSi-FUSI. Dielectric intermixing occurs without impacting the V-T uniformity, gate leakage, mobility, and reliability. Well-behaved short-channel devices (L-g similar to 100 mn, SS similar to 70 mV/dec, and DIBL similar to 65 mV/V) are demonstrated for both HfSiON and [HfSiON/Dy2O3 cap (5 angstrom)] devices with NiSi-FUSI gates, corresponding to a similar T-inv (Delta T-inv < 1 angstrom). This capping approach, when combined with Ni-silicide FUSI phase engineering, allows Delta eWF(n-p) values up to similar to 800 meV, making it promising for low-V-T CMOS.

• 出版日期2007-11