An automated high-level topology generation procedure for continuous-time Sigma Delta modulator

作者：Pandit Soumya^*; Mandal Chittaranjan; Patra Amit

来源：Integration, the VLSI Journal, 2010, 43(3): 289-304.

DOI：10.1016/j.vlsi.2010.02.001

• Analog design automation
• Analog high-level design
• Topology generation
• Sigma delta modulator

This paper presents an automated procedure for generation of high-level topologies for continuous-time Sigma Delta modulator system. A functional topology of the system is generated from the given transfer function model of the modulator. Mathematical transformation technique is applied iteratively over the initial topology to generate a functional topology which is optimized for modulator sensitivity, hardware complexity and relative power consumption. This is then implemented using behavioral models of operational transconductance amplifiers and capacitors. The generated high-level topology is ensured to work with reasonable accuracy under non-ideal conditions. The entire procedure has been implemented in Matlab/Simulink environment. Numerical results have been provided to demonstrate the procedure.

• 出版日期2010-6