A SAR-based I I" pound modulator using shared DAC

作者：Reyhani Shahbaz Z; Hashemipour Omid^*

来源：Analog Integrated Circuits and Signal Processing, 2014, 79(2): 267-276.

DOI：10.1007/s10470-014-0259-3

• Analog to digital converter
• Digital to analog converter
• Sigma Delta modulator
• Successive approximation

In this paper a new successive approximation (SA) quantizer based on the elimination of the digital to analog converter (DAC) from the quantizer structure is presented. Instead; the feedback DAC block of the I I" pound modulator is shared by SA quantizer. Using an efficient decoding algorithm in the proposed structure in conjunction with the above SA quantizer DAC elimination method, results in a reduction of the level number of the feedback DAC, and hence, a significant drop in power and area consumption is achieved. In order to study the performance of the proposed structure, a third order discrete-time I I" pound modulator is designed and simulated in 0.18 mu m CMOS technology with the following performance characteristics; a signal to noise ratio of 79.2 dB, dynamic range of 84.8 dB, power consumption of 3.75 mW and a figure of merit of 0.66 pJ/conv from a 1.8 V supply with an input signal of 200 kHz bandwidth.

• 出版日期2014-5