Novel low power reversible binary incrementer design using quantum-dot cellular automata

作者：Das, Jadav Chandra; De, Debashis^*

来源：Microprocessors and Microsystems, 2016, 42: 10-23.

DOI：10.1016/j.micpro.2015.12.004

• QCA
• Majority gate
• Peres gate
• Binary incrementer
• Quantum cost
• Reliability

This paper demonstrates the design of n-bit novel low power reversible binary incrementer in Quantum Dot Cellular Automata (QCA). The comparison of quantum cost in quantum gate based approach and in QCA based design agreed the cost efficient implementation in QCA. The power dissipation by proposed circuit is estimated, which shows that the circuit dissipates very low heat energy suitable for reversible computing. All the circuits are evaluated in terms of logic gates, circuit density and latency that confirm the faster operating speed at nano scale. The reliability of the circuit under thermal randomness is explored which describes the efficiency of the circuit.

• 出版日期2016-5