Completion Time Analysis of Wafer Lots in Single-Armed Cluster Tools With Parallel Processing Modules

作者：Lee Jun Ho; Kim Hyun Jung^*

来源：IEEE Transactions on Automation Science and Engineering, 2017, 14(4): 1622-1633.

DOI：10.1109/TASE.2017.2690443

• Cluster tool
• completion time analysis
• lot switching operation
• manufacturing scheduling
• parallel chambers

We analyze the completion time of wafer lots in single-armed cluster tools with parallel processing modules (PMs) by considering the lot switching operation. To effectively assign wafer lots and dispatch overhead hoist transports (OHTs) to manufacturing tools, it is crucial to obtain the completion time of wafer lots. However, estimating the completion time is not straightforward, due to the concurrent processing of two consecutive wafer lots during lot switching operation, which often increases wafer sojourn times in PMs. In this paper, we derive closed-form expressions of the completion time of wafer lots in single-armed cluster tools with parallel PMs. We assume that the robot unloads wafers in the order of their loading sequence. We then experimentally show that the formulas derived can be used even when processing time variation exists or another robot task sequence, which is of first-in first-out (FIFO), is assumed.
Note to Practitioners-Due to the larger wafer size and circuit width reduction, cluster tools often perform the lot switching operation with each pair of consecutive wafer lots. In addition, since most tools are operated with parallel chambers, concurrent processing with two different wafer lots occurs frequently. Such transient periods in operating tools make it hard to estimate the completion time of wafer lots. In this paper, we derive closed-form expressions to obtain the completion time of wafer lots in single-armed cluster tools with parallel chambers. We further show that the formulas can be used with processing time variation or the FIFO rule. With the formulas, OHTs can be sent just-in-time to tools to load or unload wafer cassettes, and wafer lots can be assigned while minimizing the transient periods. In addition, the estimated completion time can be utilized in the planning and scheduling of wafer fabrication processes.

• 出版日期2017-10