A System-Level Correction SAR ADC with Noise-Tolerant Technique

作者：Xu, Daiguo^*; Xu, Kaikai; Xu, Shiliu; Liu, Lu; Liu, Tao

来源：Journal of Circuits, Systems, and Computers, 2018, 27(13): 1850202.

DOI：10.1142/S021812661850202X

• Successive approximation register analog-to-digital converters (SAR ADCs)
• noise-tolerant technique
• high-speed and low-power comparator

A system-level correction successive approximation register analog-to-digital converter (SAR ADC) with regulated comparator of noise-tolerant technique is proposed. First, a substrate voltage boost technique is provided to improve the linearity and speed of sampling switch. Secondly, the proposed SAR ADC provides a comparator of noise regulation without redundant comparison cycle. The proposed comparator would be regulated in high-speed large noise state in large input differential signals. In the condition of small input differential signals, the comparator would be adjusted to low-speed small noise state. Furthermore, a high-speed low-power technique is proposed to optimize the performance of dynamic comparator. Additionally, a fast SAR logic structure is provided to increase the conversion speed of SAR ADC. To demonstrate the proposed techniques, a design example of SAR ADC is fabricated in 65 nm CMOS technology. The SAR ADC is able to tolerate about 1.1 LSB noise errors in post-simulation with the operation state regulated automatically. The core occupies an active area of only 0.025 mm(2) and consumes 1.5 mW. Measurement results achieve SFDR > 68 dB and SNDR > 57 dB, resulting in the FOM of 21.6 fJ per conversion step.

• 出版日期2018-12-15
• 单位电子科技大学