A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

作者：Marinissen Erik Jan^*; Chi Chun Chuan; Konijnenburg Mario; Verbree Jouke

来源：Journal of Electronic Testing-Theory and Applications, 2012, 28(1): 73-92.

DOI：10.1007/s10836-011-5269-9

• 3D stacked ICs
• Through-silicon via
• Manufacturing test
• Design-for-test
• Wrapper
• Test access mechanism
• Standardization
• IEEE 1149.1
• IEEE 1500

Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows pre-bond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units, which allows flexible optimization of the 3D-SIC test flow and provides yield monitoring and first-order fault diagnosis. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. Its main new component is a die-level wrapper, which can be based on either IEEE Std 1149.1 or IEEE Std 1500. The paper presents a conceptual overview of the architecture, as well as implementation aspects. Experimental results show that the implementation costs are negligible for medium to large dies.

• 出版日期2012-2
• 单位清华大学