A high-speed latched comparator with low offset voltage and low dissipation

作者：Zhu, Zhangming; Yu, Guangwen^*; Wu, Hongbing; Zhang, Yifei; Yang, Yintang

来源：Analog Integrated Circuits and Signal Processing, 2013, 74(2): 467-471.

DOI：10.1007/s10470-012-9999-0

• Latched comparator
• Positive feedback
• Transmission gate
• Monte Carlo analysis
• High-speed
• Low offset voltage
• Low dissipation

An ultra high-speed latched comparator using a controlled amount of positive feedback cell has been designed in TSMC 0.18 mu m CMOS technique. Transmission gate (TG) switches are used to implement the preamplifier circuit. The use of TG switches results in a reduction in the power consumption of the high-speed comparator as well as clock feedthrough and the effect of charge injection. The simulation results demonstrate that it can work at 1.25 GHz suitable for high speed applications, and consumes 273.6 mu W with a power supply of 1.8 V at 100 MHz and Monte Carlo simulation shows that the comparator has a low offset voltage approximately 0.499 mV.

• 出版日期2013-2
• 单位西安电子科技大学