A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands

作者：Kapadia Nishit^*; Pasricha Sudeep

来源：Integration, the VLSI Journal, 2012, 45(3): 271-281.

DOI：10.1016/j.vlsi.2011.11.010

• Networks-on-chip
• Voltage islands
• Synthesis algorithms
• Chip multiprocessor
• Core-to-tile mapping

The problem of VI-aware Network-on-Chip (NoC) design is extremely challenging, especially with the increasing core counts in today%26apos;s power-hungry Chip Multiprocessors (CMPs). In this paper, we propose a novel framework for automating the synthesis of regular NoCs with Vls, to satisfy application performance constraints while minimizing chip power dissipation. Our proposed framework uses a set of novel algorithms and heuristics to generate solutions that reduce network traffic by up to 62%, communication power by up to 32%, and total chip power dissipation by up to 13%, compared to the best known prior work that also solves the same problem.

• 出版日期2012-6