Design of Improved-Reliability Nanocircuits with Mixed NBTI- and HCI-Aware Gate-Sizing Formulation

作者：Amini sheshdeh Zhila^*; Nabavi Abdolreza

来源：IEEJ Transactions on Electrical and Electronic Engineering, 2013, 8(6): 587-590.

DOI：10.1002/tee.21900

• NBTI
• HCI
• gate
• sizing
• area

Negative bias temperature instability (NBTI) and hot carrier injection (HCI) are two important processes of reliability concern in nano-scale integrated circuits. A circuit-level design technique to combat NBTI degradation is gate oversizing. This paper presents a new technique based on PMOS and NMOS resistance variation for the NBTI- and HCI-aware gate-sizing problem for the first time. In this technique, the area of the circuit is minimized with constraints on degraded delay due to NBTI and HCI and the transitor size. Expreimental results for several gates and ISCAS%26apos;85 benchmark circuits show that this technique imposes an area overhead of less than 1% with respect to baseline design in most cases.

• 出版日期2013-11