An all-digital phase-locked loop with a PGTA-based TDC and a 0.6-V DCO

作者：Wang, Zixuan^*; Ding, Hao; Xu, Hao; Zhang, Cong; Hu, Shanwen; Ji, Xincun; Xia, Xiaojuan; Cai, Zhikuang

来源：IEICE Electronics Express, 2018, 15(22): 20180889.

DOI：10.1587/elex.15.20180889

• all digitally phase-locked loop
• time-to-digital converter
• programmable-gain time amplifier
• current-reuse

An all-digitally phase-locked loop (ADPLL) with a pipeline time-to-digital converter (TDC) is proposed in this paper. The TDC employs a programmable-gain time amplifier (PGTA) to achieve two-step time quantization. A compensator is used to correct the gain error of the PGTA. The low-voltage DCO uses current-reuse structure to achieve lower and use bridging-capacitance technique to achieve high frequency resolution. The proposed design is validated by the ADPLL fabricated in the 65-nm CMOS technology. The measurement results show that the in-band and out-band phase noises are -90 dBc/Hz@10 kHz offset and -130 dBc/Hz@1 MHz offset, respectively. The RMS and peak-peak jitter are 1.24 ps and 8.65 ps respectively.

• 出版日期2018-11-25
• 单位南京邮电大学