Dual strained channel CMOS in FDSOI architecture: New insights on the device performance

作者：Le Royer C^*; Casse M; Cooper D; Andrieu F; Weber O; Brevard L; Perreau P; Damlencourt J F; Baudot S; Previtali B; Tabone C; Allain F; Scheiblin P; Rauer C; Figuet C; Aulnette C; Daval N; Nguyen B Y; Bourdelle K K; Gyani J; Valenza M

来源：Solid-State Electronics, 2011, 65-66: 9-15.

DOI：10.1016/j.sse.2011.06.024

• CMOS
• MOSFET
• Dual channel
• Integration
• Silicon-germanium
• SOI
• Strain
• High-K
• Metal gate
• Mobility
• Access resistance
• Low-frequency noise

We report an original Dual Strained Channel On Insulator (DSCOI) Fully Depleted CMOS architecture by co-integrating nFETs on sSOI and pFETs on Si/c-SiGe/(s)SOI with a TiN/HfO(2) gate stack (EOT = 1.15 nm) and down to 40 nm gate lengths. We demonstrate for the first time large gains for transconductance (up to +125%) and mobility (+100%) even for short channel pFETs. This enables us to improve the ON(OFF) pFETs trade-off (I(ON) + 23% for a given I(OFF) = 100 nA/mu m), and thus to obtain similar I(ON) for n and pFETs (similar to 650 mu A/mu m at V(DD) = 1 V). Meanwhile, thanks to a channel material/strain engineering, the threshold voltages are adjusted (V(th) similar to +/- 0.2 V) for high performance (HP) CMOS with a single mid-gap metal gate. Extracted interface trap densities (N(T) = 5-8.5 x 10(17) cm(-3) eV(-1)) using low frequency noise indicate the excellent integrity of the TiN/HfO(2) stack when compared to SOI reference samples.

• 出版日期2011-12
• 单位中国地震局