摘要

In this article, a new on-chip power combining technique by using impedance matching Wilkinson power divider circuits will be presented. Two impedance matching Wilkinson power dividers are employed for matching the input and output impedances of the amplifier to 50 Omega as well as splitting the input power into two amplifiers and combining their output powers. A 5.2 GHz fully integrated class-A mode combined power amplifier is designed in 0.35 mu m SiGE BiCMOS technology to assess the power combining technique for WLAN applications. The power amplifier with the on-chip lumped element impedance matching Wilkinson power divider circuits has a measured small signal gain of 5.21 dB. The output power at I dB compression point is measured as 22.4 dBm, and the power added efficiency of 17% is achieved at I-dB compression point. The chip area is significantly reduced by using lumped element impedance matching Wilkinson power dividers: the total die size is 1.2 x 1.25 mm(2). including radio frequency (RE) and bias pads. The simulated (Cadence) and measured performance of combined power amplifier are well matched. Thus, the RE power amplifier and combiner/splitter circuits can be used for 5.2 GHz WLAN applications.

  • 出版日期2010-11