A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application

作者：Ko Cheng Ta^*; Hsiao Zhi Cheng; Chang Yao Jen; Chen Peng Shu; Hwang Yu Jiau; Fu Huan Chun; Huang Jui Hsiung; Chiang Chia Wen; Sheu Shyh Shyuan; Chen Yu Hua; Lo Wei Chung; Chen Kuan Neng

来源：IEEE Transactions on Device and Materials Reliability, 2012, 12(2): 209-216.

DOI：10.1109/TDMR.2012.2195005

• Hybrid bonding
• wafer level
• 3-D IC
• 3-D integration

Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In addition, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key technologies, including TSV interconnection, microbumping, hybrid bonding, wafer thinning, and backside RDL formation, were well developed and integrated to realize 3-D integration. This paper presents a complete study of the structure design, the process condition, and the electrical and reliability assessment of the wafer-level 3-D integration scheme. This 3-D integration scheme with excellent electrical performance and reliability provides a promising solution for 3-D memory application.

• 出版日期2012-6
• 单位中央民族大学