A 0.7 V Single-Supply SRAM With 0.495 mu m(2) Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

作者：Kushida Keiichi^*; Suzuki Azuma; Fukano Gou; Kawasumi Atsushi; Hirabayashi Osamu; Takeyama Yasuhisa; Sasaki Takahiko; Katayama Akira; Fujimura Yuki; Yabe Tomoaki

来源：IEEE Journal of Solid-State Circuits, 2009, 44(4): 1192-1198.

DOI：10.1109/JSSC.2009.2014009

• Low-power design
• divided bit line
• ultra-high-density cell
• SRAM

We proposed a novel SRAM architecture with a high-density cell in low-supply-voltage operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 mu m(2) cell in 65 nm CMOS technology demonstrated 0.7 V single-supply operation.

• 出版日期2009-4