Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

作者：Chen Z X^*; Yu H Y; Singh N; Shen N S; Sayanthan R D; Lo G Q; Kwong D L

来源：IEEE Electron Device Letters, 2009, 30(7): 754-756.

DOI：10.1109/LED.2009.2021079

• Gate-all-around (GAA)
• top-down
• tunneling field-effect transistor (TFET)
• vertical silicon nanowire (SiNW)

This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a Si p(+)-i-n(+) tunneling junction, the TFET with a gate length of similar to 200 nm exhibits good subthreshold swing of similar to 70 mV/dec, superior drain-induced-barrier-lowering of similar to 17 mV/V, and excellent I(on)-I(off) ratio of similar to 10(7) with a low I(off) (similar to 7 pA/mu m). The obtained 53 mu A/mu m I(on) can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.

• 出版日期2009-7