A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration

作者：Daigneault Marc Andre^*; David Jean Pierre

来源：IEEE Transactions on Instrumentation and Measurement, 2011, 60(6): 2070-2079.

DOI：10.1109/TIM.2011.2115390

• Dynamic reconfiguration
• field-programmable gate array (FPGA)
• time-interval measurement
• time-to-digital converter (TDC)

A high-resolution high-precision time-to-digital converter (TDC) architecture is presented for implementation on field-programmable gate arrays (FPGAs) supporting dynamic reconfiguration. The proposed architecture relies on multiple parallel high-resolution delay lines implemented by the programmable interconnection points within the routing switch fabric. These delay lines feature a 1-ps resolution over a range of 3 ns. A calibration process is proposed to take process-voltage-temperature variations, as well as clock skew, into account. A TDC with a 50-ps resolution and precision as high as 35 ps has been implemented on a Virtex-II Pro FPGA. Results show that the proposed architecture and calibration process can be used to achieve resolutions as fine as 10 ps.

• 出版日期2011-6