A digital calibration technique for charge pumps in phase-locked systems

作者：Liang Che Fu^*; Chen Shin Hua; Liu Shen Iuan

来源：IEEE Journal of Solid-State Circuits, 2008, 43(2): 390-398.

DOI：10.1109/JSSC.2007.914283

• charge pump (CP) calibration
• digital calibration
• frequency synthesizer
• phase-locked loop (PLL)

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked systems. In this digital calibration technique, there is no extra replica CP needed. In addition, it can calibrate the CP under different control voltages on the loop filter to be immune to the channel-length modulation. Due to the digital nature, the additional power consumption and digital switching noise from the calibration circuits are turned off once the calibration is finished. A 5 GHz frequency synthesizer is used to justify the proposed calibration technique. The measured output spur is suppressed by 5.35 dB at 5.2 GHz after the calibration circuits are active. The measured output spur levels are less than -68.5 dBc throughout the whole output frequency range. The measured phase noise is -110 dBc/Hz at an offset frequency of 1 MHz.

• 出版日期2008-2
• 单位中国科学院电工研究所