Novel Circuit Technique for Reduction of Leakage Current in Series/Parallel PMOS/NMOS Transistor Stack

作者：Neema Vaibhav^*; Chouhan Shailesh Singh; Tokekar Sanjiv

来源：IETE Journal of Research, 2010, 56(6): 362-366.

DOI：10.4103/0377-2063.76206

• Active mode
• Leakage current
• Transistor stacking
• Standby mode

Stacking of MOS transistors is used for minimization of leakage current in nano-scale Complementary Metal Oxide Semiconductor (CMOS) circuits. Stack arrangement of P-Channel Metal Oxide Semiconductor (PMOS) is preferred over N-Channel Metal Oxide Semiconductor (NMOS) because value of leakage current in PMOS is lesser as compared to NMOS. It results as the mobility of holes in PMOS is lesser than mobility of electrons in NMOS. This paper leads us to an observation of leakage current consumption by series/parallel combination of PMOS/NMOS transistors. This observation results in the development of novel circuit technique for reduction of leakage current in series/parallel PMOS/NMOS assembly. The effect of V(GS), V(DS), V(SB) and intermediates node voltages is also addressed. The proposed circuit is simulated for Model file BSIM 3 Ver. 3.1, TSMC 0.18 mu m technology using Spice c simulator.

• 出版日期2010-12