A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT Delta Sigma ADC With Anti-Pole-Splitting Opamp and Digital I/Q Calibration

作者：Xu, Yang^*; Zhang, Zehong; Chi, Baoyong; Qi, Nan; Cai, Hualin; Wang, Zhihua

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(1): 243-255.

DOI：10.1109/TVLSI.2015.2394365

• Amplifier
• antipole splitting
• continuous time (CT)
• delta-sigma (Delta Sigma) modulator
• excess loop delay (ELD)
• I/Q calibration
• power scaling technique (PST)
• quadrature bandpass (QBP)
• reconfigurable

A dual-mode second-order reconfigurable quadrature bandpass continuous-time delta-sigma modulator is presented for a low-IF global navigation satellite system receiver to simplify the entire architecture. The proposed modulator is capable of supporting both narrowband of 5-MHz bandwidth (BW) and wideband of 20-MHz BW. An amplifier topology with active feed-forward and antipole-splitting compensation schemes is proposed. The flexible amplifiers in active-RC integrators and preamplifiers in comparators are implemented with power scaling technique to effectively adjust the power consumption for both BWs. A 1-bit digitally switched current digital-to-analog converter structure with gate-leakage compensation and low-latency dynamic element matching is proposed to cover large current variations and mitigate the gate-leakage issue. Digital I/Q self-calibration algorithm is realized to improve the image-rejection ratio (IRR). Implemented in 65-nm CMOS, the Delta Sigma modulator achieves 67.8-/61.4-dB dynamic range, 65.9-/53.7-dB signal-to-noise-plus-distortion ratio, and >60-dB IRR after calibration across 5-/20-MHz BW with center frequencies of 4/12 MHz, respectively. Powered by a 1.2 V supply, the modulator only consumes 4.2/8.1 mW, resulting in measured figure-of-merits of 0.26/0.51 pJ/conversion step.

• 出版日期2016-1
• 单位清华大学