A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique

作者：Lin Chin Yu; Lee Tai Cheng

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2016, 63(7): 929-938.

DOI：10.1109/TCSI.2016.2546856

• FoM
• foreground calibration
• inter-stage DAC error
• passive residue transfer technique
• pipelined-SAR ADC
• 2.8-bit SAR

A 12-bit 210-MS/s 2-channel time-interleaved analog-to-digital converter (ADC) employing a pipelined-SAR architecture for low-power and high-speed application is presented. The proposed ADC is partitioned into 3 stages with a passive residue transfer technique between the 1st and 2nd stages for power saving and active residue amplification between the 2nd and 3rd stages for noise consideration. Furthermore, a 2.8-bit SAR conversion embedded in the 1st stage also improves the speed and downsizes the required decoupling capacitance of reference voltage. With the foreground calibration, the inter-stage DAC error and gain/offset errors between interleaving channels are resolved. The proposed ADC, fabricated in a 65-nm CMOS technology, consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.5 dB at low input frequencies and 60.1 dB near Nyquist rate. The prototype occupies an active area of 0.48 mm2 and the corresponding FoM is 30.3 fJ/conversion-step.

• 出版日期2016-7