摘要

An effective supply voltage monitor evaluates dynamic variation of (V-dd-V-ss) within power rails of integrated circuits on a die. The monitor occupies an area of as small as 10.8 x 14.5 mu m(2) and is followed by backend digitizing circuits, both using 3.3 V thick oxide transistors in a 65 nm CMOS technology for covering all power domains from core circuits to peripheral I/O rings. A prototype demonstrates capturing of effective supply voltage waveforms in digital (shift registers) as well as in analog (4 bit Flash ADC) circuits.

  • 出版日期2013-4

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