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摘要
This paper describes the design of 5-GHz fully integrated self-biasing power amplifier (PA) for wireless transmitter applications in a 0.18-mu m CMOS technology. The proposed class-E PA employs the cascode topology with a self-biasing technique to reduce device stress. Three cascaded class-D driver amplifiers are used to actualize the sharp switching at the class-E power stage. All device components are integrated on chip and the chip area is 1.0x1.3mm(2). The measurement results indicate that the PA delivers 16.4 dBm output power and 35.4% power-added efficiency with 2.3V power supply voltage into a 50 Omega load.
- 出版日期2013
