A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

作者：Shaker Mohamed O^*; Bayoumi Magdy A

来源：Journal of Circuits, Systems, and Computers, 2014, 23(2): 1450023.

DOI：10.1142/S0218126614500236

• Clock gating
• layout simulations
• successive approximation register

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPEC-TRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

• 出版日期2014-2