A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology

作者：Hou Yu^*; Chen Zhijie; Miyahara Masaya; Matsuzawa Akira

来源：IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2016, E99A(12): 2473-2482.

DOI：10.1587/transfun.E99.A.2473

• Op-ampfree
• SAR
• VCO
• hybrid
• 1-1 MASH ADC

This paper proposes a SAR-VCO hybrid 1-1 MASH ADC architecture, where a fully-passive 1st-order noise-shaping SAR ADC is implemented in the first stage to eliminate Op-amp. A VCO-based ADC quantizes the residue of the SAR ADC with one additional order of noise shaping in the second stage. The inter-stage gain error can be suppressed by a foreground calibration technique. The proposed ADC architecture is expected to accomplish 2nd-order noise shaping without Op-amp, which makes both high SNDR and low power possible. A prototype ADC is designed in a 65nm CMOS technology to verify the feasibility of the proposed ADC architecture. The transistor-level simulation results show that 75.7dB SNDR is achieved in 5MHz bandwidth at 60MS/s. The power consumption is 748.9 W under 1.0V supply, which results in a FoM of 14.9fJ/conversion-step.

• 出版日期2016-12