An Ultra-Low-Energy Analog Comparator for A/D Converters in CMOS Image Sensors

作者：Jendernalik Waldemar^*

来源：Circuits, Systems, and Signal Processing, 2017, 36(12): 4829-4843.

DOI：10.1007/s00034-017-0630-6

• CMOS
• Analog comparator
• Voltage-to-time converter
• Slope analog-to-digital converter
• CMOS image sensor
• Energy consumption

This paper proposes a new solution of an ultra-low-energy analog comparator, dedicated to slope analog-to-digital converters (ADC), particularly suited for CMOS image sensors (CISs) featuring a large number of ADCs. For massively parallel imaging arrays, this number may be as high as tens-hundreds of thousands ADCs. As each ADC includes an analog comparator, the number of these comparators in CIS is always high. Detailed analysis shows that power dissipation of a comparator contributes significantly to a total power consumption of an ADC. Thus, minimization of the comparator energy consumption during the analog-to-digital (A/D) conversion of an image frame is crucial for design of CMOS image sensors. Compared to classical dynamic or continuous-time comparators operating in the slope ADC, under the same bias conditions, the proposed comparator shows a 2-3 orders of magnitude reduction of the power consumption. In addition, the proposed topology shows a simple and compact layout and does not require a power-down mechanism. The circuit has been simulated in detail for a 0.18-mu m CMOS technology under two different power supply voltages of 1.8 and 1 V. While implemented in a 12-bit slope ADC of a massively parallel CIS, operating at a speed 1000 fps, the energy required for A/D conversion is 0.5 pJ.

• 出版日期2017-12