A 1-V, 330-nW, 6-Bit Current-Mode Logarithmic Cyclic ADC for ISFET-Based Digital Readout System

作者：Thanachayanont Apinunt^*

来源：Circuits, Systems, and Signal Processing, 2015, 34(5): 1405-1429.

DOI：10.1007/s00034-014-9908-0

• Ion-sensitive FET
• Logarithmic ADC
• Subthreshold
• Cyclic ADC
• pH readout circuit

This paper describes the design and implementation of a low-power current-mode logarithmic analog-to-digital converter (ADC) for an ISFET-based digital readout system. The system comprises a front-end ISFET-based readout circuit and a succeeding logarithmic ADC to produce a digital output signal which is linearly related to the input variation. The front-end readout circuit is realized using a subthreshold ISFET/REFET differential pair with a current-mode translinear multiplier/divider circuit. The logarithmic ADC is realized using the cyclic architecture and current-mode circuit techniques to achieve low power dissipation. High-accuracy current sample-and-hold circuit based on the regulated-cascode switched-current memory cell and low-power high-resolution current comparator are proposed for the ADC realization. All circuits were designed to operate with a single 1-V power supply voltage, and were simulated with process parameters from a 0.18-m CMOS technology. The power dissipation of the front-end readout circuit and the logarithmic ADC is 20 and 330 nW, respectively. The front-end readout circuit can produce an output current range of 0.1-300 nA which is logarithmically corresponded to the input range of 4-10. The logarithmic ADC operates with 1-kS/s sampling rate and achieves the integral nonlinearity error of LSB, the effective number of bits of 5.95, and 37.6-dB of signal-to-noise-distortion ratio with 100-nA full-scale input range.

• 出版日期2015-5