A single-channel 8-bit 660 MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS

作者：Zhu, Zhangming^*; Liu, Minjie; Wang, Qiyu; Yang, Yintang

来源：MICROELECTRONICS JOURNAL, 2014, 45(7): 880-885.

DOI：10.1016/j.mejo.2014.04.039

• Successive approximation register (SAR)
• A/D converter
• High speed
• CMOS
• Asynchronous logic circuits
• Pre-setting procedure

A single-channel 8-bit low-power high-speed SAR ADC with a novel pre-settling procedure is presented in this paper. The proposed procedure relaxes the settling time significantly and improves the speed of the ADC. Moreover, the asynchronous technique avoids the high frequency internal clocks and further increases the speed of the SAR ADC. Based on SMIC 65 nm 1.2-V CMOS technology, the simulation results demonstrate that DNL and INL are 0.4/0.4 LSBs and 0.9/0.8 LSBs, respectively. At 660 MS/s sampling rate, the ADC consumes 7.6 mW from a 1.2 V supply. The proposed SAR ADC's SNDR and SFDR are 49.5 dB and 64.2 dB, respectively.

• 出版日期2014-7
• 单位西安电子科技大学