A Digital PLL Using Oversampling Delta-Sigma TDC

作者：Wei Chih Lu; Liu Shen Iuan^*

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63(7): 633-637.

DOI：10.1109/TCSII.2016.2530904

• Bang-bang phase-frequency detector (BBPFD)
• delta-sigma
• digital phase-locked loop (DPLL)
• time-to-digital converter (TDC)

A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter (Delta Sigma TDC) is presented. This Delta Sigma TDC adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed Delta Sigma TDC consumes 0.519 mW at a supply of 1.1 V, and its area is 0.0027 mm(2). The measured output frequency is 4 GHz, and the division ratio is 128. The power of the DPLL is 3.51 mW, and its rms jitter is 861 fs.

• 出版日期2016-7
• 单位中国科学院电工研究所