Analysis of the Spur Characteristics of Edge-Combining DLL-Based Frequency Multipliers

作者：Casha Owen^*; Grech Ivan; Badets Franck; Morche Dominique; Micallef Joseph

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2009, 56(2): 132-136.

DOI：10.1109/TCSII.2008.2011605

• Delay mismatch
• delay-locked loop (DLL)
• frequency synthesis
• in-lock error
• spurious level

A complete analysis of the spur characteristics of edge-combining delay-locked loop (DLL)-based frequency multipliers is presented in this brief. The novelty of this analysis is the fact that it can be used to estimate the effect of both the in-lock error and the delay-stage mismatch on the spurious level of the frequency multiplier with low computational complexity. In addition, a way to reduce the mismatch between the delay cells in the delay line is discussed via an analytic model and verified by the implementation of a delay cell in a 65-nm CMOS process.

• 出版日期2009-2
• 单位中国地震局